Method for implementing a segmented current-mode digital/analog converter with matched segment time constants
US6621439B1 · kind B1 · utility
17Cited by
5References
28Claims
0Family size
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Key dates
| Filing date | Apr 25, 2002 |
| Grant date | Sep 16, 2003 |
| Priority date | — |
| Expiry date | Apr 25, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/747
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method for implementing segmented digital-analog converters (DACs) operating in the current mode matches the time constants in the most-significant-bit (MSB) segments to the time constants in the (LSB) least-significant-bit segments, and any intermediate-significant-bit (ISB) segments. The method can be implemented using the simple addition of capacitances or the resizing of transistors in the circuit at appropriate points. The resulting DAC exhibits high dynamic linearity and spurious free dynamic range (SFDR).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.