High speed, low power switched-capacitor digital-to-analog converter with a precharge arrangement
US6621444B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 17, 2002 |
| Grant date | Sep 16, 2003 |
| Priority date | — |
| Expiry date | Jun 17, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/804
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A switched capacitor digital-to-analog converter includes a first voltage generator for providing first and second reference voltages, a second voltage generator for providing third and fourth reference voltages selected to match predetermined design values of the first and second reference voltages, and an array of binary weighted capacitors. Each capacitor has a first electrode connected to a common circuit node, which is connected to a converter output terminal and a second electrode selectively connected, through an associated first switching circuit, to either one of the first and second reference voltages or, through an associated second switching circuit, to either one of the third and fourth reference voltages. The converter includes a circuit for monitoring the values of each bit of input digital codes, and a control circuit coupled to the first and second switching circuits to open or close selectively during a bit clock period the connections to the first, second, third, and fourth voltages according to the following criterion: when a bit value of the current input digital code Bj is equal to the corresponding bit value of the previous input digital code Bj−1, the …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.