Low power reference buffer circuit utilizing switched capacitors
US6621445B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 24, 2002 |
| Grant date | Sep 16, 2003 |
| Priority date | — |
| Expiry date | Jun 24, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C27/024
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A reference buffer circuit includes a first switched capacitor selectively coupled to a first node that receives a reference voltage from a buffer device connected to the first node. A second switched capacitor is selectively coupled to a voltage source to receive a charging voltage from the voltage source. A first switch is coupled to the first switched capacitor to switch communication of the first switched capacitor between the first node and a second node. And, a second switch is coupled to the second switched capacitor to switch communication of the second switched capacitor between the voltage source and the first node, wherein the second switched capacitor delivers the charging voltage to the first switched capacitor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.