Biasing technique for a high density SRAM
US6621726B2 · kind B2 · utility
3Cited by
3References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 13, 2001 |
| Grant date | Sep 16, 2003 |
| Priority date | — |
| Expiry date | Jan 15, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/412
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to one embodiment, a memory cell is disclosed. The memory cell includes a first PMOS transistor, a first NMOS transistor coupled to the first PMOS transistor, a second PMOS transistor and a second NMOS transistor coupled to the first PMOS transistor. The first and second PMOS transistors receiving a bias control signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.