Three-transistor SRAM device
US6621727B2 · kind B2 · utility
Inventor
Key dates
| Filing date | Jan 4, 2002 |
| Grant date | Sep 16, 2003 |
| Priority date | — |
| Expiry date | Feb 22, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/41
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A three-transistor SRAM device are disclosed. The SRAM device has an NMOS with its source connected to a first voltage source and its substrate connected to a second voltage source. The source of the NMOS is connected either a constant voltage source or a variable voltage source. An PMOS and the NMOS form a common node A. The drain of the NPMOS is connected to the source of the PMOS to form a common node B. A resister is connected between the nodes A and B. Another NMOS is connected between the node B and a bit line. The gate of this NMOS is controlled by a word line. A capacitor type amplifier may be further connected to the node B to form the data latch of the SRAM.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.