Semiconductor memory device using only single-channel transistor to apply voltage to selected word line
US6621735B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 8, 2001 |
| Grant date | Sep 16, 2003 |
| Priority date | — |
| Expiry date | Jun 8, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device disclosed herein comprises a memory cell array in which memory cells are arranged in a matrix and a row decoder circuit for selecting a word line in this memory cell array and for applying a voltage to the selected word line. The decoder circuit includes a plurality of first transistors of a first conductivity type in which one end of each current path is directly connected to each of the word lines, and a second transistor of a second conductivity type opposite to the first conductivity type for applying a voltage to a gate of the first transistor connected to a selected word line at the time of the operation for applying a voltage to the selected word line. The application of a voltage to the selected word line is performed only by the first transistor of the first conductivity type.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.