Semiconductor memory
US6621750B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 28, 2002 |
| Grant date | Sep 16, 2003 |
| Priority date | — |
| Expiry date | May 28, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/848
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A redundancy memory circuit stores a defect address indicating a defective memory cell row. A redundancy control circuit disables the defective memory cell row corresponding to the defect address stored in the redundancy memory circuit and enables a redundancy memory cell row in the memory block containing the defective memory cell row. Moreover, in the other memory blocks, the redundancy control circuit disables memory cell rows corresponding to the defective memory cell row and enables redundancy memory cell rows instead of these memory cell rows. Consequently, not only the memory block having the defective memory cell row but one of the memory cell rows in the other memory blocks is always also relieved. Thus, the redundancy memory circuit can be shared among all the memory blocks with a reduction in the number of redundancy memory circuits. As a result, the semiconductor memory can be reduced in chip size.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.