Method and apparatus for adjusting the clock delay in systems with multiple integrated circuits
US6621882B2 · kind B2 · utility
5Cited by
15References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 2, 2001 |
| Grant date | Sep 16, 2003 |
| Priority date | — |
| Expiry date | Feb 11, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0816
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for adjusting the clock delay in systems with multiple integrated circuits has a controller, a programmable clock generator and a plurality of integrated circuits, each integrated circuit including a data flip-flop, a programmable delay and a clock-fanout tree, wherein the clock delay in the integrated circuits is adjusted to match the inherent delay in the integrated circuit having the longest inherent delay.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.