Buffer associated with multiple data communication channels
US6622186B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 17, 1999 |
| Grant date | Sep 16, 2003 |
| Priority date | — |
| Expiry date | Dec 17, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/103
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A buffer for adapting data flows from input channels to output channels is provided. The buffer includes a DRAM organized in blocks and a memory controller for managing assignment of the blocks to the chains of linked blocks. The DRAM contains, as a chain of linked blocks, data associated with each communication channel formed by a pair of input and output channels, and also contains a main queue of free blocks for listing unoccupied blocks. The memory controller includes a cache memory containing a partial queue of free blocks that the memory controller uses in managing block assignment. According to one embodiment, when a level of the partial queue reaches a predetermined minimum limit the cache memory is at least partially filled by a burst from the main queue, and when a level of the partial queue reaches a predetermined maximum limit the cache memory is at least partially emptied by a burst into the main queue. According to another embodiment, the partial queue stores a local image of a top portion of the main queue, and the memory controller exclusively uses the partial queue in assigning blocks to the chains of linked blocks. Further embodiments of the present invention prov…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.