Embedded memory access method and system for application specific integrated circuits
US6622203B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 29, 2001 |
| Grant date | Sep 16, 2003 |
| Priority date | — |
| Expiry date | Jul 27, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/104
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An application specific integrated circuit (ASIC) architecture for memory access. A first functional block provides a first address, a first column address strobe signal, and a first read/write signal associated with a first memory access. A second functional block provides a second address, a second column address strobe signal, and a second read/write signal associated with a second memory access. The ASIC architecture includes an embedded memory interface that is coupled to the first functional block and the second functional block. The embedded memory interface provides the first functional block and the second functional block access to an embedded memory either at the same time (referred to herein as concurrent access or simultaneous access) or at different times (referred to herein as consecutive or non-concurrent access). When predetermined conditions are met, the embedded memory interface provides the first functional block and the second functional block concurrent access to the embedded memory. When the predetermined conditions are not met, the embedded memory interface provides consecutive access to the embedded memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.