Method for controlling write cache transfer and disk unit
US6622206B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 9, 2000 |
| Grant date | Sep 16, 2003 |
| Priority date | — |
| Expiry date | Oct 10, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0866
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system are disclosed to prevent significant degradation of a data transfer rate in write cache transfer, thereby keeping the minimum data transfer rate high. The initial value Ti of the virtual buffer full capacity T(tx) is set to F/N (where F is a data capacity of the buffer, and N>1) and it is determined if the amount of write cached data S(tx) reaches the virtual buffer full capacity T(tx) so that write cache transfer is enabled during an S(tx)<T(tx) period and if virtual buffer full (S(tx)=T(tx)) is satisfied, the write cache transfer is inhibited until S(tx)<T(tx) is satisfied and the virtual buffer full capacity T(tx) is increased by a predetermined value K from the current one each time disk writing is stopped (each time a write error occurs) while the virtual buffer full is continued, thereby enabling write cache transfer while disk writing is stopped.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.