System and methods using a system-on-a-chip with soft cache
US6622208B2 · kind B2 · utility
19Cited by
14References
18Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 30, 2001 |
| Grant date | Sep 16, 2003 |
| Priority date | — |
| Expiry date | Mar 30, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1045
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A soft cache system compares tag bits of a virtual address with tag fields of a plurality of soft cache register entries, each entry associated with an index to a corresponding cache line in virtual memory. A cache line size for the cache line is programmable. When the tag bits of the virtual address match the tag field of one of the soft cache entries, the index from that entry is selected for generating a physical address. The physical address is generated using the selected index as an offset to a corresponding soft cache space in memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.