Two-way cache system and method for interfacing a memory unit with a peripheral device using first and second cache data regions
US6622213B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 15, 2001 |
| Grant date | Sep 16, 2003 |
| Priority date | — |
| Expiry date | Jan 15, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0846
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A two-way cache system for interfacing with a peripheral device and a method of operating a two-way cache system for carrying out data transmission between a peripheral device and a memory unit. The cache system has a two-way first-in first-out buffer region and a two-way cache controller. The two-way first-in first-out buffer region further has a first cache data region and a second cache data region. The first cache data region and the second cache data region are capable of holding a batch of first cache data and a batch of second cache data. The two-way cache controller receives a read request from the peripheral device. According to the read request, the requested data and data that ensues or comes after the requested data are retained by the two-way first-in first-out buffer (FIFO) region. If the peripheral device continues to request more data by maintaining a FRAME signal line in an enabled state, the first cache data region and the second cache data region are alternately used to read in subsequent data. A check may be made to see if requested data stored inside the two-way cache buffer region is coherent or consistent with data stored inside the memory unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.