Mechanism for handling conflicts in a multi-node computer architecture
US6622215B2 · kind B2 · utility
2Cited by
3References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 29, 2000 |
| Grant date | Sep 16, 2003 |
| Priority date | — |
| Expiry date | Jan 18, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0831
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to one embodiment, a method is disclosed. The method includes receiving a first request from a first node in a multi-node computer system to invalidate a first cache line at a second node. The method also includes receiving a second request from the second node to invalidate the first cache line at the first node and detecting the concurrent requests at conflict detection circuitry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.