Method of making field effect transistor in which the increase of parasitic capacitance is restrained by scale reduction
US6624034B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 19, 2002 |
| Grant date | Sep 23, 2003 |
| Priority date | — |
| Expiry date | Jun 19, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0212
Abstract
A method of producing a semiconductor device includes forming a gate electrode on a channel region on a surface of a semiconductor region of a semiconductor substrate, the channel region having a depth in the semiconductor substrate; forming a first pair of side wall spacers on opposite sides of the gate electrode; forming elevated semiconductor layers, each elevated semiconductor layer being elevated relative to the channel region, on regions outside of the pair of side wall spacers and in which source and drain regions of a first conductivity type are to be formed; removing the pair of first side wall spacers; and forming a pair of pocket injection regions of a second conductivity type by introducing, after the side wall spacers are removed, a dopant impurity producing the second conductivity type deeper in the semiconductor substrate than a region where the side wall spacers were formed, the pair of pocket injection regions respectively covering only a neighborhood of respective side surface parts of the channel region, where the source and drain regions are to be formed, forming respective pn junctions only between the neighborhood of the side surface parts and the pocket injec…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.