Methods and apparatus for providing improved physical designs and routing with reduced capacitive power dissipation
US6624056B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 4, 2001 |
| Grant date | Sep 23, 2003 |
| Priority date | — |
| Expiry date | Dec 4, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques are described for semiconductor chips with reduced capacitive power dissipation as a result of improved conductor line spacing. The approaches are particularly applicable to 0.25 micron chip design processes and below. According to one aspect, where there are n available metallization layers available to the designer, a smaller number of layers, such as n−1, are utilized initially in developing a routing design. Then, at least one further metallization layer is used to systematically route conductors, such as bus conductors, to increase the number of metal pitches between conductors, by promoting conductors from one layer to another.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.