High frequency field effect transistor with carrier extraction to reduce intrinsic conduction
US6624451B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 21, 2001 |
| Grant date | Sep 23, 2003 |
| Priority date | — |
| Expiry date | Nov 10, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/824
Abstract
A field effect transistor (FET) is of the type which employs base biasing to depress the intrinsic contribution to conduction and reduce leakage current. It incorporates four successive layers (102 to 108): a p+ InSb base layer (102), a p+ InAlSb barrier layer (104), a &pgr; intrinsic layer (106) and an insulating SiO2 layer (108); p+ source and drain regions (110, 112) are implanted in the intrinsic layer (106). The FET is an enhancement mode MISFET (100) in which biasing establishes the FET channel in the intrinsic layer (106). The insulating layer (108) has a substantially flat surface supporting a gate contact (116). This avoids or reduces departures from channel straightness caused by intrusion of a gate groove, and enables a high value of current gain cut-off frequency to be obtained. In FETs with layers that are not flat, departures from channel straightness should not be more than 50 nm in extent, preferably less than 5 nm.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.