Implant method for forming Si3N4 spacer
US6624466B2 · kind B2 · utility
3Cited by
8References
3Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 12, 2002 |
| Grant date | Sep 23, 2003 |
| Priority date | — |
| Expiry date | Feb 12, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
Abstract
A method is disclosed to form a reliable silicon nitride spacer between the lower edges of the floating gate and the control gate of a split-gate flash memory cell. This is accomplished by forming a floating gate with vertical sidewalls, forming a high temperature oxide layer followed by silicon nitride layer over the floating gate including the vertical sidewalls, ion implanting the nitride layer and then selectively etching it to form a robust silicon nitride spacer of well defined rectangular shape.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.