Method and apparatus for dynamically controlling the performance of buffers under different performance conditions
US6624655B2 · kind B2 · utility
4Cited by
7References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 9, 2002 |
| Grant date | Sep 23, 2003 |
| Priority date | — |
| Expiry date | Dec 9, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00078
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
According to one aspect of the invention, a method is provided in which an input signal is received at a first node of a buffer circuit. The propagation of the input signal from the first node to a second node in the buffer circuit is delayed by a delay period based upon a first control input. The delay period is adjusted by a factor based upon a second control input.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.