High speed voltage mode differential digital output driver with edge-emphasis and pre-equalization
US6624670B2 · kind B2 · utility
17Cited by
3References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 14, 2002 |
| Grant date | Sep 23, 2003 |
| Priority date | — |
| Expiry date | May 25, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/03878
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A differential driver includes two feedback loops 20 and 22, and two inverter pairs 24 and 26. The two feedback loops 20 and 22 regulate the source voltages for the two inverter pairs 24 and 26 to the reference voltages VREFHI and VREFLO. The two inverter pairs 24 and 26 switch the output load RL and CL between the two regulated voltages in response to the input voltages IN+ and IN−. The reference voltages VREFHI and VREFLO are created by a reference cell and set the output high and low voltages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.