Free-running mode device for phase locked loop
US6624675B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 11, 2001 |
| Grant date | Sep 23, 2003 |
| Priority date | — |
| Expiry date | May 11, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/033
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A P-stage shift register or counter is added to the charge pump and/or to the phase frequency detector of a phase locked loop circuit to keep the output clock stable enough from the locked frequency value and available for long enough after the input reference clock has been removed. This mode is called the phase locked loop (PLL) free running mode (FRM) and is activated as soon as the device has detected the loss of the input reference clock of the phase locked loop. Once the free running mode is activated the charge pump automatically enters its high impedance state resulting in a slower frequency shift process at the PLL output in comparison to a conventional PLL. This main advantage of this PLL circuit is that the system clock is kept running for long enough so that the system can issue a fault report through another logic and memory device when the reference clock is suddenly removed either accidentally or not.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.