Control circuit for phase-locked loop (PLL) with reduced cycle slip during acquisition of phase lock
US6624705B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 4, 2002 |
| Grant date | Sep 23, 2003 |
| Priority date | — |
| Expiry date | Apr 20, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/1072
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit for controlling a phase-locked loop (PLL) with reduced cycle slip during acquisition of phase lock includes frequency dividers with selectable divisors for the reference and feedback signals, and a phase detector having a charge pump output circuit with selectable output current ranges. During acquisition of phase lock by the PLL, the divisors for the reference and feedback signal frequency dividers are increased by the same factor, and the charge pump current range is increased by the same ratio. As a result, the reference rate is decreased as the charge pump current range is increased simultaneously by the same ratio. Meanwhile, the linear loop bandwidth and phase margin remain substantially constant.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.