Offset calibration system
US6624772B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 28, 2002 |
| Grant date | Sep 23, 2003 |
| Priority date | — |
| Expiry date | May 28, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/02
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An offset calibration system includes an analog to digital converter having a first full-scale range with a first offset compensation circuit; a digital to analog converter having a second full-scale range with a second offset compensation circuit; the digital to analog converter having its output connected to the input of the analog to digital converter during calibration of the digital to analog converter; and a range adjustment circuit for accumulating a predetermined number of analog to digital output values and dividing the accumulated values by a preselected power of 2 in the ratio of the voltage corresponding to the analog to digital converter least significant bit to the voltage corresponding to the digital to analog converter least significant bit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.