Method and apparatus for adjustment of time delays in synchronous clocked bus systems
US6625176B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 29, 1999 |
| Grant date | Sep 23, 2003 |
| Priority date | — |
| Expiry date | Apr 29, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04Q2213/13389
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A method is provided to adjust time delays and sequence ordering of data channels in synchronous clocked bus systems. In particular, the invention relates to a method to re-synchronize data in respective channels which have a relative delay to each other caused by different path lengths, etc., on the way from sender to receiver. Still more specifically, the invention relates to an apparatus used to eliminate those delays in order to make data usable again on the receiver side. The method can be carried out using standard microprocessors without the need for special hardware implementations. Thus the use of costly and performance intensive ASICs and signal processors can be avoided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.