Cycle modeling in cycle accurate software simulators of hardware modules for software/software cross-simulation and hardware/software co-simulation
US6625572B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 22, 1999 |
| Grant date | Sep 23, 2003 |
| Priority date | — |
| Expiry date | Dec 22, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2117/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Clock cycle simulation involves modeling of clock cycles in a hardware module with a software model. Each simulated clock cycle involves several individual stages: Start, Execute, and End. During the start stage, output pin values for the model are calculated from an initial state of the module being simulated. Between the start stage and the execution stage, a combinatorial function of the modules outputs can be calculated. These calculated functions may be used as inputs to the modules in the execution stage. Afterwards, during the execute stage, input pin values are received by the model and the next state of the module is calculated based upon the current module state and the input pin values. Finally, during the last stage, i.e., the end stage, the internal state is updated; the internal state is defined as a set of the module's internal register and memory values.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.