Unified renaming scheme for load and store instructions
US6625723B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 7, 1999 |
| Grant date | Sep 23, 2003 |
| Priority date | — |
| Expiry date | Jul 7, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/384
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer architecture for collapsing dependency graphs for colliding store and load instructions. Many-to-one mappings are provided between logical registers and physical registers, so that more than one logical register may map to the same physical register. For a load instruction that is predicted to collide with an earlier in-flight store instruction, the destination logical register of the load instruction is mapped to the same physical register to which the source logical register of the earlier in-flight store instruction is mapped. A many-to-one mapping may be realized by associating a counter with each physical register, so that the value of a counter indicates whether its associated physical counter is free.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.