Method and apparatus to support an expanded register set
US6625724B1 · kind B1 · utility
51Cited by
4References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 28, 2000 |
| Grant date | Sep 23, 2003 |
| Priority date | — |
| Expiry date | Mar 28, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/34
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Processors and methods having an expanded logical register set are disclosed. A processor includes may include Intel Architecture-32 (IA-32) instruction set decoding logic and an expanded logical register set. The expanded logical register set may include more than eight logical registers of a first type. An expanded register set decoding logic, coupled to said IA-32 instruction set decoding logic, may determine that an instruction includes an at least four-bit register identifier, the at least four-bit register identifier to specify one logical register of said expanded logical register set.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.