Firmware mechanism for correcting soft errors
US6625749B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 21, 1999 |
| Grant date | Sep 23, 2003 |
| Priority date | — |
| Expiry date | Dec 21, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/845
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system includes processor having dual execution cores and a non-volatile memory that stores an error recovery routine. The processor's execution cores operate in lock step when the processor is in a redundant execution mode, and they operate independently when the processor is in a split execution mode. The error recovery routine is invoked when the processor detects a soft error while operating in the redundant execution mode. The error recovery routine switches the processor to split execution mode. In split mode, each execution core saves uncorrupted processor state data to a designated memory location and updates any corrupted data with corresponding processor state data from the other execution core. The error recovery routine returns the processor to redundant mode, initializes each execution core with the recovered processor state data, and returns control of the processor to the program thread that was executing when the soft error was detected.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.