Method and device for collecting output logic values from a logic unit in an electronic circuit
US6625767B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 26, 2000 |
| Grant date | Sep 23, 2003 |
| Priority date | — |
| Expiry date | Apr 26, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318552
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method and device for collecting logic values output from a logic unit having n inputs and p outputs included within an electronic circuit is provided by p test cells. These test cells are connected in parallel respectively to the p outputs of the logic unit such that the logic values of the outputs of the logic unit are loaded into the test cells in a normal mode, and are connected in series with each other to form a shift register for propagating logic values of the outputs of the logic unit to a collecting node in a test mode. In a first phase, the logic values of one out of two outputs of the logic unit are propagated to the shift register. Then, in a second phase, the logic values of the other outputs of the logic unit are propagated in the shift register. The logic values of the outputs of the logic unit are reloaded in the test cells between the first and second phase.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.