Test bus architecture
US6625768B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 29, 2000 |
| Grant date | Sep 23, 2003 |
| Priority date | — |
| Expiry date | Mar 29, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31926
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A test bus architecture for testing an integrated circuit having a plurality of agents includes providing both a test block select signal and test function select signal to a plurality of select decoders respectively disposed in each of the plurality of agents. The test block select signal has a number of states at least equal to the number of agents and the test function select signal at least equal to a maximum number of internal signal groups of any one of the agents, each select decoder having at least one internal signal group which is outputted from circuitry to be tested within the agent of the select decoder. An output from each of the select decoders is fed to a test bus output such that a selected internal signal group is outputted to the test bus output upon the agent of the selected signal group being selected by the state of the test block select signal and the selected signal group being selected by the state of the test function select signal by the select decoder.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.