Redundancy system and method for locating errors in interleaved code words
US6625774B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 29, 1999 |
| Grant date | Sep 23, 2003 |
| Priority date | — |
| Expiry date | Oct 29, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/1515
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An iterative method and system are disclosed for locating errors in interleaved code words. The system and method generate column parity check symbols using symbols from selected columns in the interleaved code words. The width of each column parity check symbol is reduced, followed by the reduced column parity check symbols being merged to create merged column check symbols. A Reed-Solomon encoding algorithm is performed on the merged column check symbols to generate error locating check symbols which are combined with the reduced column parity check symbols to create an error locating code word. The error locating check symbols are stored with the interleaved code words in memory. Following retrieval from memory, the error locating code word is reconstructed and decoded upon the detection of at least one uncorrectable interleaved code word from decoding the interleaved code words. Errors identified from decoding the error locating code word are marked as erasures in the appropriate columns of the interleaved code words. Decoding of the previously uncorrectable interleaved code words is subsequently performed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.