Superlattice structures having selected carrier pockets and related methods

US6627809B1 · kind B1 · utility

Assignee

• Massachusetts Institute of Technology · US

Inventors

• Takaaki Koga · Cambridge, US
• Mildred Dresselhaus · Arlington, US
• Xiangzhong Sun · Cambridge, US
• Steven B. Cronin · Cambridge, US

Key dates

• Filing date: Nov 9, 2000
• Grant date: Sep 30, 2003
• Expiry date: Nov 9, 2020

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10N10/8556

Abstract

A carrier pocket engineering technique used to provide superlattice structures having relatively high values of the three-dimensional thermoelectric figure of merit (Z3DT) is described. Also described are several superlattice systems provided in acordance with the carrier pocket engineering technique. Superlattice structures designed in accordance with this technique include a plurality of alternating layers of at least two different semiconductor materials. First ones of the layers correspond to barrier layers and second ones of the layers correspond to well layers but barrier layers can also work as well layers for some certain carrier pockets and vice-versa. Each of the well layers are provided having quantum well states formed from carrier pockets at various high symmetry points in the Brillouin zone of the structure to provide the superlattice having a relatively high three-dimensional thermoelectric figure of merit.