Linearized folding amplifier
US6628167B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 23, 2002 |
| Grant date | Sep 30, 2003 |
| Priority date | — |
| Expiry date | Oct 23, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/445
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A linearized folding amplifier circuit (30) includes a comparator (40) that has a first state and a second state, and a switched output circuit that has a pair of outputs. The non-linearity in the response of a differential transistor pair to an input signal is partially linearized by a first resistor connecting the emitters of the two input transistors. The input is further linearized in response to the first and second state-controlling pairs of transistors and a differential error voltage therebetween that is replicated from the differential error in the base-voltages emitter voltages of the input differential pair. The output of the circuit is the combination of the partially linearized portion from the first resistor and a linearized transconductor circuit that has an output formed in response to the differential error.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.