Data and clock extractor with improved linearity
US6628173B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 2001 |
| Grant date | Sep 30, 2003 |
| Priority date | — |
| Expiry date | Feb 26, 2022 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S331/02
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Phase-locked-loop based data and clock extraction comprising a phase detector that generates up and down pulses. Down pulses are maintained in width approximately equal to 1.5 unit intervals of a local sampling clock. Up pulses are allowed to vary with the phase relationship between the local sampling clock and an incoming encoded bit stream. The up pulses are allowed to vary between 1 and 2 unit intervals of the local sampling clock. The up and down pulses drive a charge pump D/A converter that generates a control voltage. The control voltage sets the frequency of the local sampling clock generated by a voltage controlled oscillator. Shift register controlled by a state machine and clocked by the local clock allows reception of complex data packets arriving by the encoded bit stream.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.