Distributed averaging analog to digital converter topology
US6628224B1 · kind B1 · utility
14Cited by
16References
33Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 24, 2002 |
| Grant date | Sep 30, 2003 |
| Priority date | — |
| Expiry date | May 24, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/365
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An analog to digital converter includes a first amplifier array connected to taps from a reference ladder, a second amplifier array, wherein each amplifier in the first amplifier array is connected to only two amplifiers of the second amplifier array, a third amplifier array, wherein each amplifier in the second amplifier array is connected to only two amplifiers of the third amplifier array, and an encoder connected to outputs of the third amplifier array that converts the outputs to an N-bit digital signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.