Method of arrangement to determine a clock timing error in a multi-carrier transmission system, and a related synchronization units
US6628738B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 22, 1998 |
| Grant date | Sep 30, 2003 |
| Priority date | — |
| Expiry date | Sep 22, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L27/2675
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
In a multi-carrier transmission system, a clock timing error (&tgr;e) is calculated at the receiver's side and used for synchronization between a transmitting modem and a receiving modem (RX1). The clock timing error (&tgr;e) is calculated from phase errors (&phgr;0, &phgr;1, . . . , &phgr;i, . . . , &phgr;N-1) detected for a plurality of pilot carriers during a tracking mode in such a way that the share (Ai) of a phase error (&phgr;i) detected for a particular pilot carrier in the clock timing error (&tgr;e) depends on the transmission quality (SNRi) of that pilot carrier over the transmission medium in between the two modems. In this way, the robustness of the synchronization for narrowband noise near a pilot carrier is improved significantly.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.