Message signaled interrupt generating device and method
US6629179B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 31, 2000 |
| Grant date | Sep 30, 2003 |
| Priority date | — |
| Expiry date | Sep 13, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides a bridge device and a method for generating message signaled interrupts to indicate completion of write transactions from one or more secondary bus devices to a primary bus device. The bridge device is coupled between a first bus and a second bus. The one or more secondary bus devices are coupled to the second bus and the primary bus device is coupled to the first bus. The bridge device includes a bridge FIFO and control circuitry, a first register, and an interrupt generation logic. The bridge FIFO and control circuitry is arranged to control data transfer between the one or more secondary bus devices and the primary bus device. The bridge FIFO and control circuitry is further configured to store and transfer write data from the one or more secondary bus devices to the primary bus device. The first register is arranged to store a set of interrupt bit numbers. Each of the one or more secondary bus devices is configured to write an interrupt bit number into the first register after completion of a write data transfer to the bridge FIFO and control circuitry to indicate completion of the write data transfer. The interrupt generation logic is coupled to …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.