Method and apparatus for improving read latency for processor to system memory read transactions
US6629217B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 22, 1999 |
| Grant date | Sep 30, 2003 |
| Priority date | — |
| Expiry date | Dec 22, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/161
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for improving read latency for processor to system memory read transactions is disclosed. One embodiment of a system logic device includes logic that assumes a transfer size of a predetermined length. In this manner, the system logic device can issue a read transaction request to system memory as soon as the read request address is delivered by the processor rather than waiting for the processor to deliver information indicating the transfer length. Once the actual transfer length information is delivered from the processor to the system logic device, the system logic device determines whether any of the data returned by the system memory needs to be purged before returning the requested data to the processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.