Message index descriptor
US6629229B1 · kind B1 · utility
0Cited by
7References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 24, 2001 |
| Grant date | Sep 30, 2003 |
| Priority date | — |
| Expiry date | May 8, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/387
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit comprising a memory, a queue, and a translator. The memory may be configured to store a message at an address at least as great as a base address. The queue may be configured to store a descriptor, wherein the descriptor is configured to have (i) an index, (ii) a routing field, and (iii) fewer bits than the address. The translator may be configured to translate between the address and the index.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.