Determining transistor widths using the theory of logical effort
US6629301B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 15, 2000 |
| Grant date | Sep 30, 2003 |
| Priority date | — |
| Expiry date | Jan 9, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3308
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for finding suitable transistor sizes for complex logic networks. An electrical “logical effort model” of a logic circuit is made by replacing each logic element with a simple electrical model and retaining the wiring topology of the original circuit. The logical effort model is a DC circuit with parameters that depending only on the gain chosen for the logic elements in the critical path, the stray capacitance of critical connections, and the logical effort of each logic element. A circuit simulation of the logical effort model produces voltages proportional to desired transistor widths. In working on the electrical model, the circuit simulator merely solves the set of simultaneous equations implied by the model. Alternate methods are also described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.