High-performance laminate for integrated circuit interconnection
US6630628B2 · kind B2 · utility
4Cited by
7References
21Claims
0Family size
Assignee
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Key dates
| Filing date | Feb 7, 2002 |
| Grant date | Oct 7, 2003 |
| Priority date | — |
| Expiry date | Feb 7, 2022 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T428/24917
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A high-performance, integrated circuit interconnection laminate. Power/ground layers in laminates fabricated with open areas to permit out gassing of gases generated during high temperature lamination are located such that they do not lie under/over critical traces on signal layers. This placement of the open areas enables a reduction in cross-talk between signal layers lying on opposite sides of a power/ground layer and a reduction in signal delay.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.