NMOS circuit in isolated wells that are connected by a bias stack having pluralirty of diode elements
US6630700B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 5, 2001 |
| Grant date | Oct 7, 2003 |
| Priority date | — |
| Expiry date | Oct 5, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/85
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated NMOS circuit including an active stack having a plurality of isolated p-well active devices M1-M3, a bias stack having a plurality of diode-connected isolated p-well bias devices M4-M6, the gate of each of the plurality of diode-connected isolated p-well bias devices coupled to the gate of a corresponding one of the plurality of isolated p-well active devices, the bulk of each of the plurality of diode-connected isolated p-well bias devices coupled directly to the bulk of the corresponding one of the plurality of isolated p-well active devices, and the source of each of the plurality of diode-connected isolated p-well bias devices coupled directly to the bulk of the corresponding diode-connected isolated p-well bias device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.