Hardened MOS transistors
US6630719B2 · kind B2 · utility
5Cited by
7References
40Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 6, 2000 |
| Grant date | Oct 7, 2003 |
| Priority date | — |
| Expiry date | Dec 6, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/611
Abstract
A lateral MOS transistor including a gate and drain and source regions of a first conductivity type formed in a substrate of a second conductivity type connected to a first power supply, wherein a doped buried layer of the first conductivity type extends under said drain region and under a portion of the gate, the buried layer being connected to the gate via a one-way connection.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.