Digital frequency divider with a single shift register
US6630849B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 13, 2002 |
| Grant date | Oct 7, 2003 |
| Priority date | — |
| Expiry date | Mar 13, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K23/66
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A digital frequency divider has a single circulating shifter register loaded with a bit sequence of variable length and having two outputs adjacent such that are output is equal to the other delayed by one clock period. The outputs are passed to a multiplexer via further logic, the multiplexer selecting one of two inputs depending on whether a clock is high or low. Program logic is provided so that the circuit is configurable for odd, even or half integer division by detecting changes in the bit sequence between 0 and 1 and selectively “deleting” the first half clock cycle when a change is detected. This allows even, odd or half integer clock division with an “even” mark space ratio.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.