Programmable phase locked-loop filter architecture for a range selectable bandwidth
US6630860B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 20, 2000 |
| Grant date | Oct 7, 2003 |
| Priority date | — |
| Expiry date | Sep 20, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H2210/036
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A programmable phase locked-loop (PLL) active filter circuit is provided which includes networks of cooperating bandwidth tuning components to select bandwidth ranges. The values and arrangement of the network of selectable series input (R1) resistors are chosen to be useful in both low band and high band settings. Likewise, the opamp network of feedback resistors (R2) and capacitors (C1) values are chosen to be useful in both low band and high band applications, automatically pairing with the R1 selection in response to a bandwidth range selection. These tuning components, internal to an integrated circuit, can be used for a plurality of wideband loops. External components can be used to supplement the internal components for low and high bandwidth applications.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.