Low voltage single poly deep sub-micron flash eeprom
US6631087B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 9, 2001 |
| Grant date | Oct 7, 2003 |
| Priority date | — |
| Expiry date | Dec 12, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/685
Abstract
An EEPROM memory cell comprising a transistor on a first conductivity type semiconductor substrate and a capacitor formed on a second conductivity type semiconductor substrate. The capacitor comprises first and second injector regions of third conductivity type, a channel region of second conductivity type separating the first and second injector regions and a first electrically floating structure disposed above the channel region, wherein a first edge portion of the floating structure overlaps a portion of the first injector region and a second edge portion of the first floating structure overlaps a portion of the second injector region, and a control gate region of fourth conductivity type located within the second conductivity type semiconductor substrate region. The gate structure and first floating structure are electrically connected together. In different aspects of the present invention, the EEPROM memory cell may also include a second capacitor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.