System and method for a mixer circuit with anti-series transistors
US6631257B1 · kind B1 · utility
19Cited by
4References
69Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 20, 2000 |
| Grant date | Oct 7, 2003 |
| Priority date | — |
| Expiry date | Apr 20, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03D2200/0088
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A system and method for a mixer circuit places the RF and mixer core LO transistors on the same level in anti-series. The mixer circuit provides increased headroom, excellent linearity, controllable conversion-gain, and operates with a reduced supply voltage requirement.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.