Method and apparatus for speculative addition using a limited carry
US6631393B1 · kind B1 · utility
3Cited by
2References
11Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 31, 1997 |
| Grant date | Oct 7, 2003 |
| Priority date | — |
| Expiry date | Jun 28, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/5063
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
One embodiment of the present invention, an eight bit binary adder with a typical latency independent of its width, is described. The adder comprises a four bit adder for calculating bits S3-S0 of the sum, plus four bitslice circuits, one for speculatively calculating each of bits S7-S4 of the sum. The calculation of the carry bit out of each bitslice is limited to the operands bits into that bitslice and the three preceding bitslices. Each bitslice also includes circuitry for detecting a potential error in the speculative sum such that the speculative sum can be corrected when there is a potential error.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.