Embedded system with interrupt handler for multiple operating systems
US6631394B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 20, 1999 |
| Grant date | Oct 7, 2003 |
| Priority date | — |
| Expiry date | Jan 20, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/45533
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An embedded system (1) comprising at least one processor (2) for running an operating system (OS_A, OS_B). The embedded system (1) further comprises:means (17, 401, 412) for running at least two operating systems (OS_A, OS_B) in said processor (2),a first operating system (OS_A) comprising a first group of threads (THA1, THA2, THA_IDLE),a second operating system (OS_B) comprising a second group of threads (THB1, THB2, THB_IDLE),means (nFIQ, nIRQ, SWI) for generating an interrupt (FIQ, IRQ, SWI) to said processor (2),means for examining (401, 603, 617) to the execution of which thread (THA1, THA2, THB1, THB2, THA_IDLE, THB_IDLE) the interrupt (FIQ, IRQ, SWI), that has come to the processor (2), affects, andmeans (401, 412, 603, 609, 617) for transmitting interrupt data to said operating system (OS_A, OS_B) which relates to the thread (THA1, THA2, THB1, THB2, THA_IDLE, THB_IDLE) affecting the interrupt (FIQ, IRQ, SWI) received by the processor (2).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.