Method and apparatus for scheduling memory calibrations based on transactions
US6631440B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 30, 2000 |
| Grant date | Oct 7, 2003 |
| Priority date | — |
| Expiry date | May 27, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/161
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system includes a memory controller that controls and formats transactions with a high speed memory. The memory controller includes a read queue, a write queue, and various other queues in which memory transactions may be stored pending execution. The memory controller periodically executes calibration cycles, such as temperature calibration cycles to the memory to reduce memory errors. The temperature calibration cycles may include an idle state during which no read transactions can be executed. The memory controller includes arbitration logic that reduces latency by issuing read transaction first. Once reads have been issued, the arbitration logic executes any pending temperature cycles. During the idle period of the calibration cycle, the arbitration logic schedules write transactions, and transactions to memory from other queues and devices, including precharge transactions, row activate transactions, refresh cycles, and other calibration cycles.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.